Design Verification Engineer

Project Description:

As Design Verification Engineer, you will join leading-edge team responsible for the verification of advanced interconnect systems in state-of-the-art microprocessors. This role focuses on ensuring the functionality, performance, and reliability of high-bandwidth data communication architectures.

We are looking for someone who has a passion for modern, complex processor architecture, digital design, and verification in general. Who are a team player and has good communication skills, strong analytical and problem-solving skills and willing to learn and ready to accept challenges.

Skills required:

-Minimum of 5 years experience in Digital Design Verification
-Strong skills with System Verilog and UVM. Good skills with Verilog
-Exposure to both maintaining an existing Verification Environment as well as creating one from scratch
-Experience with functional verification tools by VCS, Cadence, Mentor Graphics
-Experience working in a Unix/Linux environment
-Good scripting skills (Perl, Shell, Ruby)

Nice To Have:

-Proven experience of working with complex designs (not just I2C and other similar designs) would be an asset
-Good computer architecture, cache coherency knowledge would be an asset
-Exposure to simulation profile, efficiency improvement, acceleration would be an asset
-Exposure to leadership or mentorship would be an asset

Responsibilities:

-Perform pre-Silicon Verification of next generation high performance Microprocessor designs and related IPs
-Develop, document and execute on verification test plans at unit level of design hierarchy
-Develop high level language testbench components including stimulus drivers, behavioral models, monitors and checkers in SystemVerilog
-Develop, simulate and debug directed/random stimulus to ensure design functionality according to specifications